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FM25040A Datasheet(PDF) 7 Page - Ramtron International Corporation |
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FM25040A Datasheet(HTML) 7 Page - Ramtron International Corporation |
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7 / 13 page  FM25040A Rev. 3.0 May 2006 Page 7 of 13 The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The BP1 and BP0 bits allow software to selectively write protect the array. These settings are only used when the /WP pin is inactive and the WREN command has been issued. The following table summarizes the write protection conditions. Table 4. Write Protection WEL /WP Protected Blocks Unprotected Blocks Status Register 0 X Protected Protected Protected 1 0 Protected Protected Protected 1 1 Protected Unprotected Unprotected Memory Operation The SPI interface, with its relatively high maximum clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25040A can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The bus master then issues a WRITE op- code. Part of this op-code includes the upper bit of the memory address. Bit 3 in the op-code corresponds to A8. The next byte is the lower 8-bits of the address A7-A0. In total, the 9-bits specify the address of the first byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFh is reached, the counter will roll over to 000h. Data is written MSB first. Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). The rising edge of /CS terminates a WRITE op-code operation. Read Operation After the falling edge of /CS, the bus master can issue a READ op-code. Part of this op-code includes the upper bit of the memory address. The next byte is the lower 8-bits of the address. In total, the 9-bits specify the address of the first byte of the read operation. After the op-code is complete, the SI pin is ignored. The bus master then issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFh is reached, the counter will roll over to 000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation.. The bus configuration for read and write operations is shown below. Hold The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master takes the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state. |
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Similar Description - FM25040A |
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