SN54LV08, SN74LV08

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS186C – FEBRUARY 1993 – REVISED APRIL 1996

1

POST OFFICE BOX 655303

CMOS) 2-

µ Process

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Per JEDEC Standard JESD-17

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW), and

Ceramic Flat (W) Packages, Ceramic Chip

Carriers (FK), and Ceramic (J) 300-mil DIPs

description

These quadruple 2-input positive-AND gates are

Y = A

) B in positive logic.

The SN74LV08 is available in TI’s shrink

small-outline package (DB), which provides the

same I/O pin count and functionality of standard

small-outline packages in less than half the

printed-circuit-board area.

The SN54LV08 is characterized for operation over the full military temperature range of – 55

°C to 125°C. The

SN74LV08 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

H

H

L

XL

X

L

L

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

SN54LV08 ...J OR W PACKAGE

SN74LV08 . . . D, DB, OR PW PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

SN54LV08 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Copyright

© 1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.