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HD66789 Datasheet(PDF) 69 Page - Renesas Technology Corp |
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HD66789 Datasheet(HTML) 69 Page - Renesas Technology Corp |
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69 / 156 page  HD66789 Preliminary Rev.0.12, May 09 2003, page 69 of 156 Reset Function The HD66789 makes internal initialization with RESET input. During RESET, the HD66789 is in a busy state, and no instruction from the MPU and access to GRAM are accepted. The time required for the RESET input is at least 1ms. In case of power-on reset, wait at least 10ms after the power is turned on until the R-C oscillation frequency becomes stabilized. While waiting, do not make an initial setting for the instruction set or an access to GRAM. Initial State of Instructions a. Start oscillation b. Driver output control (NL4–0 = “11101”, SS = “0”, SM = “0”, EPL = “0”, DPL = “0”, HSPL = “0”, VSPL = “0”, GS = “0”, SM = “0”) c. Liquid crystal AC drive control (FLD1-0 = “01”, B/C = “0”, EOR = “0”, NW5–0 = “00000”) d. Entry mode set (HWM = “0”, I/D1-0 = “11”: Increment by 1, AM = “0” : Horizontal direction, LG2–0 = “000” : Replace mode, BGR = “0”, TRI = “0”, DFM1-0 = “00”) e. Compare register (CP17–0 : “00 0000 0000 0000 0000”) f. Display control 1 (PT1-0 = “00”, VLE2-1 = “00” : No vertical scroll, SPT = “0”, FRCP = “0”, DTE = “0”, CL = “0” : 65,536-color mode, REV = “0”, D1-0 = “00” : Display OFF, GON = 0) g. Display control 2 (BP3-0 = “1000”, FP3-0 = “1000”) h. Display control 3 (PTG1-0 = “00”, ISC3-0 = “0000” i. Frame cycle control (NO1-0 = “00”, SDT1-0 = “00”, EQ1-0 = “00” : No equalization, DIV1-0 = “00”: clock/1, RTN3-0 = “0000” : 16 clocks in 1H period) j. External display interface (RIM1-0 = “00” : 18-bit RGB interface, DM1-0 = “00” : internal clock operation, RM = “0” : System interface) k. Power control 1 (SAP2-0 = “000”, BT2-0 = “000”, AP2–0 = “000”: liquid crystal power supply off, DK = “1” : DCDC1 off, SLP = “0”, STB = “0” : Standby mode off) l. Power control 2 (DC12-0 = “000”, DC02-00 = “000”, VC2-0 = “000”) m. Power control 3 (PON = “0”, VRH3-0 = “00000”) n. Power control 4 (VCOMG = “0”, VDV4-0 = “00000”, VCM4-0 = “00000”) o. RAM address set (AD15–0 = “0000”H) p. RAM write data mask (WM17–0 = “18’h00000”: No mask) q. γ control (PKP02-00 = “000”, PKP12-10 = “000”, PKP22-20 = “000”, PKP32-30 = “000”, PKP42-40 = “000”, PKP52-50 = “000”, PRP02-00 = “000”, PRP12-10 = “000”) (PKN02-00 = “000”, PKN12-10 = “000”, PKN22-20 = “000”, PKN32-30 = “000”, PKN42-40 = “000”, PKN52-50 = “000”, PRN02-00 = “000”, PRN12-10 = “000”) (VRP14-10 = “00000”, VRP03-00 = “0000”, VRN14-10 = “00000”, VRN12-10 = “000”) r. Gate scan starting position (SCN4-0 = “00000”) s. Vertical scroll (VL7–0 = “00000000”) t. 1st split-screen (SE17-10 = “11111111”, SS17-10 = “00000000”) u. 2nd split-screen (SE27-20 = “11111111”, SS27-20 = “00000000”) v. Horizontal RAM address position (HEA7-0 = “10000011”, HSA7-0 = “00000000”) w. Vertical RAM address position (VEA7-0 = “10101111”, VSA7-0 = “00000000”) |
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