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CD74ACT280EE4 Datasheet(PDF) 1 Page - Texas Instruments |
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CD74ACT280EE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 12 page 1 Data sheet acquired from Harris Semiconductor SCHS250A Features • Buffered Inputs • Typical Propagation Delay - 10ns at VCC = 5V, TA = 25 oC, C L = 50pF • Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015 • SCR-Latchup-Resistant CMOS Process and Circuit Design • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption • Balanced Propagation Delays • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50 Ω Transmission Lines Description The ’AC280 and ’ACT280 are 9-bit odd/even parity genera- tor/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even par- ity is indicated ( ∑E output is HIGH) when an even number of data inputs is HIGH. Odd parity is indicated ( ∑O output is HIGH) when an odd number of data inputs is HIGH. Parity checking for words larger than nine bits can be accom- plished by tying the ∑E output to any input of an additional ’AC280, ’ACT280 parity checker. Pinout CD54AC280, CD54ACT280 (CERDIP) CD74AC280, CD74ACT280 (PDIP, SOIC) TOP VIEW Functional Diagram Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54AC280F3A -55 to 125 14 Ld CERDIP CD74AC280E 0 to 70oC, -40 to 85, -55 to 125 14 Ld PDIP CD74AC280M 0 to 70oC, -40 to 85, -55 to 125 14 Ld SOIC CD54ACT280F3A -55 to 125 14 Ld CERDIP CD74ACT280E 0 to 70oC, -40 to 85, -55 to 125 14 Ld PDIP CD74ACT280M 0 to 70oC, -40 to 85, -55 to 125 14 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all elec- trical specifications. Please contact your local TI sales office or cus- tomer service for ordering information. I6 I7 NC I8 ∑E ∑O GND VCC I5 I4 I3 I2 I1 I0 1 2 3 4 5 6 7 14 13 12 11 10 9 8 8 9 10 11 13 2 1 12 5 6 ∑ ODD ∑ EVEN I0 I1 I2 I3 I5 I6 I7 I4 4 I8 GND = 7 VCC = 14 NC = 3 August 1998 - Revised May 2000 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated CD54/74AC280, CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker |
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