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TPS54377 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS54377 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 21 page  www.ti.com VOUT PH Vin TOPSIDEGROUND AREA VIA toGroundPlane ANALOGGROUNDTRACE EXPOSED PowerPAD AREA COMPENSATION NETWORK OUTPUTINDUCTOR OUTPUT FILTER CAPACITOR BOOT CAPACITOR INPUT BYPASS CAPACITOR INPUT BULK FILTER FREQUENCY SETRESISTOR SLOWSTART CAPACITOR BIASCAPACITOR BOOT COMP PWRGD PH PH PH PH SS/ENA VBIAS VIN VIN VIN PGND PGND TPS54377 SLVS779 – SEPTEMBER 2007 The TPS54377 has two internal grounds (analog and The PH pins should be tied together and routed to power). Inside the TPS54377, the analog ground ties the output inductor. Since the PH connection is the to all of the noise sensitive signals, while the power switching node, inductor should be located very close ground ties to the noisier power signals. Noise to the PH pins and the area of the PCB conductor injected between the two grounds can degrade the minimized to prevent excessive capacitive coupling. performance of the TPS54377, particularly at higher Connect the boot capacitor between the phase node output currents. Ground noise on an analog ground and the BOOT pin as shown. Keep the boot capacitor plane can also cause problems with some of the close to the IC and minimize the conductor trace control and bias signals. For these reasons, separate lengths. analog and power ground traces are recommended. There should be an area of ground on the top layer Connect the output filter capacitor(s) as shown directly under the IC, with an exposed area for between the VOUT trace and PGND. It is important to connection to the PowerPAD. Use vias to connect keep the loop formed by the PH pins, LO, CO and this ground area to any internal ground planes. Use PGND as small as practical. additional vias at the ground side of the input and Place the compensation components from the VOUT output filter capacitors as well. The AGND and PGND trace to the VSENSE and COMP pins. Do not place pins should be tied to the PCB ground by connecting these components too close to the PH trace. Due to them to the ground area under the device as shown. the size of the IC package and the device pinout, The only components that should tie directly to the they must be routed close, but maintain as much power ground plane are the input capacitors, the separation as possible while still keeping the layout output capacitors, the input voltage decoupling compact. capacitor, and the PGND pins of the TPS54377. Use a separate wide trace for the analog ground signal Connect the bias capacitor from the VBIAS pin to path. This analog ground should be used for the analog ground using the isolated analog ground voltage set point divider, timing resistor RT, slow start trace. The bias capacitor should be as close as capacitor and bias capacitor grounds. Connect this possible to the VBIAS pin and analog ground . If a trace directly to AGND (pin 1). slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency, connect them to this trace. Figure 11. TPS54377 PCB Layout Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS54377 |
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