MT48H16M16LFB5-8G datasheet(1/71 Pages) MICRON

Part #	MT48H16M16LFB5-8G

Description	256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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Products and specifications discussed herein are subject to change by Micron without notice.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

PDF:09005aef8219eeeb/Source: 09005aef8219eedd

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT48H16M16LF__1.fm - Rev F 4/07 EN

1

Mobile SDRAM

MT48H16M16LF – 4 Meg x 16 x 4 banks

MT48H8M32LF – 2 Meg x 32 x 4 banks

Features

• Fully synchronous; all signals registered on positive

edge of system clock

•VDD/VDDQ = 1.70–1.95V

• Internal, pipelined operation; column address can

be changed every clock cycle

• Four internal banks for concurrent operation

• Programmable burst lengths: 1, 2, 4, 8, or continuous

page1

• Auto precharge, includes concurrent auto precharge

• Auto refresh and self refresh modes

• LVTTL-compatible inputs and outputs

• On-chip temperature sensor to control refresh rate

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Selectable output drive (DS)

• 64ms refresh period (8,192 rows)

Notes: 1. For continuous page burst, contact factory

for availability.

Options

Marking

•VDD/VDDQ

– 1.8V/1.8V

H

•Configuration

– 16 Meg x 16 (4 Meg x 16 x 4 banks)

16M16

– 8 Meg x 32 (2 Meg x 32 x 4 banks)

8M32

•Plastic “green” package

– 54-ball VFBGA (8mm x 9mm)

BF

– 90-ball VFBGA (8mm x 13mm)

B5

• Timing – cycle time

– 7.5ns at CL = 3

-75

– 8ns at CL = 3

-8

•Power

– Standard IDD2P/IDD7None

– Low IDD2P/IDD7L

• Operating temperature range

– Commercial (0° to +70°C)

None

– Industrial (–40°C to +85°C)

IT

•Design revision

:G

Table 1:

Addressing

16 Meg x 16

8 Meg x 32

Configuration

4 Meg x 16 x 4

banks

2 Meg x 32 x 4

banks

Refresh count

8K

Row addressing

8K (A0–A12)

4K (A0–A11)

Bank addressing

4 (BA0, BA1)

Column addressing

512 (A0–A8)

Table 2:

Key Timing Parameters

CL = CAS (READ) latency

Speed

Grade

Clock Rate

(MHz)

Access Time

Data

Setup

Time

Data

Hold

Time

CL = 2 CL = 3 CL = 2 CL = 3

-75

104

133

8ns

6ns

1.5ns

1ns

-8

100

125

9ns

7ns

2.5ns

1ns

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	MT47H128M16RT-25EITC	1Mb / 134P	DDR2 SDRAM MT47H512M4 ??64 Meg x 4 x 8 banks MT47H256M8 ??32 Meg x 8 x 8 banks MT47H128M16 ??16 Meg x 16 x 8 banks
	MT47H128M16RT-25EC	1Mb / 134P	DDR2 SDRAM MT47H512M4 ??64 Meg x 4 x 8 banks MT47H256M8 ??32 Meg x 8 x 8 banks MT47H128M16 ??16 Meg x 16 x 8 banks
	MT47H64M16HR-25H	1Mb / 132P	DDR2 SDRAM MT47H256M4 ??32 Meg x 4 x 8 banks MT47H128M8 ??16 Meg x 8 x 8 banks MT47H64M16 ??8 Meg x 16 x 8 banks
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MT48H16M16LFB5-8G Datasheet(PDF) 1 Page - Micron Technology

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