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MT48H16M16LFBF-8G Datasheet(PDF) 5 Page - Micron Technology

Part # MT48H16M16LFBF-8G
Description  256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT48H16M16LFBF-8G Datasheet(HTML) 5 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT48H16M16LF_2.fm - Rev F 4/07 EN
5
©2006 Micron Technology, Inc. All rights reserved.
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
General Description
Figure 1:
256Mb Mobile SDRAM Part Numbering
General Description
The Micron® 256Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access
memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512
columns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4,096 rows by
512 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BLs) of 1, 2, 4, or 8
page locations with a read burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. It also allows the column address to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide seamless high-speed, random-
access operation.
Speed Grade
tCK = 7.5ns
tCK = 8.0ns
-75
-8
IT
Operating Temp.
Commercial
Industrial
L
Power
Standard IDD2P/IDD7
Low IDD2P/IDD7
Example Part Number: MT48H8M32LFB5-75LIT
Mobile
Configuration
MT48
Package
Speed
Temp.
Power
Configuration
16 Meg x 16
8 Meg x 32
16M16LF
8M32LF
Package
8 x 9 VFBGA (lead-free)
8 x 13 VFBGA (lead-free)
H
VDD/
VDDQ
VDD/VDDQ
1.8V/1.8V
BF
B5
Revision
Revision
:G Design Revision


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