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EL7158ISZ-T13 Datasheet(PDF) 8 Page - Intersil Corporation |
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EL7158ISZ-T13 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 9 page 8 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7349.2 May 14, 2007 Applications Information Product Description The EL7158 is a high performance 40MHz pin driver. It contains two analog switches connecting VH and VL to OUT. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied which opens both switches simultaneously. Due to the topology of the EL7158, both the VH and VL pins can be connected to any voltage between the VS+ and VS- pins, but VH must be greater than VL in order to prevent turning on the body diode at the output stage. Three-State Operation When the OE pin is low, the output is three-state (floating). The output voltage is the parasitic capacitance’s voltage. It can be any voltage between VH and VL, depending on the previous state. At three-state, the output voltage can be pushed to any voltage between VH and VL. The output voltage can’t be pushed higher than VH or lower than VL since the body diode at the output stage will turn on. Supply Voltage Range and Input Compatibility The EL7158 is designed for operation on supplies from 5V to 18V (4.5V to 18V maximum). Table 2 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. All input pins are compatible with both 3V and 5V CMOS signals. With a positive supply (VS+) of 5V, the EL7158 is also compatible with TTL inputs. Power Supply Bypassing When using the EL7158, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7158 necessitate the use of a bypass capacitor between the supplies (VS+ and VS-) and GND pins. It is recommended that a 2.2µF tantalum capacitor be used in parallel with a 0.1µF low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7158 is driving highly capacitive loads. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL7158 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (+125°C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type. Power dissipation may be calculated: where: VS is the total power supply to the EL7158 (from VS+ to GND) VOUT is the swing on the output (VH - VL) CL is the load capacitance CINT is the internal load capacitance (100pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application’s power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below TJMAX: where: TJMAX is the maximum junction temperature (+125°C) TMAX is the maximum operating temperature PD is the power dissipation calculated above θJA thermal resistance on junction to ambient θJA is 160°C/W for the SOIC8 package when using a standard JEDEC JESD51-3 single-layer test board. If TJMAX is greater than +125°C when calculated using Equation 2 , then one of the following actions must be taken: Reduce θJA the system by designing more heat-sinking into the PCB (as compared to the standard JEDEC JESD51-3) De-rate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (TMAX) PD V S ( I S ) C INT ( V S 2 f ) C L ( V OUT 2 f ) × × + × × + × = (EQ. 1) θ JA T JMAX T MAX – PD ----------------------------------------- = (EQ. 2) EL7158 |
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Similar Description - EL7158ISZ-T13 |
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