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SN65LVDT33DR Datasheet(PDF) 10 Page - Texas Instruments |
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SN65LVDT33DR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 23 page  www.ti.com VIA VIB VO –100 mV @ 250 KHz –32 mV @ 250 KHz Failsafe Asserted VIA VIB VO a) No Failsafe b) Failsafe Asserted td1 td2 1.4 V 1 V 0.4 V 0 V –0.4 V VOH 1.4 V VOL –0.2 V >1.5 µs SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 Table 1. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages APPLIED VOLTAGES(1) RESULTANT INPUTS VIA (mV) VIB (mV) VID (mV) VIC (mV) Output –4000 –3900 –100 –3950 L –4000 –3968 –32 –3984 H 4900 5000 –100 4950 L 4968 5000 –32 4984 H (1) These voltages are applied for a minimum of 1.5 µs. Figure 5. VIT3 Failsafe Threshold Test Figure 6. Waveforms for Failsafe Activate and Deactivate 10 Submit Documentation Feedback |
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