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MB90M407APF Datasheet(PDF) 2 Page - Fujitsu Component Limited. |
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MB90M407APF Datasheet(HTML) 2 Page - Fujitsu Component Limited. |
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2 / 64 page  MB90M405 Series 2 • Command structure optimized for controller applications • Able to handle following data types : bit, byte, word, and long word • 23 types of addressing mode • High code efficiency (compiler) • Enhanced calculation precision using a 32-bit accumulator • Enhanced signed multiplication and division instructions and RETI instructions • Command structure supports C language/multitasking • Employs system stack pointers • Instruction set had symmetry and barrel shift instruction functions • Program patch functions (2-address pointers) • Improved execution speed • 4-byte built-in instruction queue allows instructions to be read ahead of time, speeding up execution. • Interrupt function • 8 programmable priority level settings • Incorporates powerful 32-factor interrupt function • Data transfer function • Extended intelligent I/O service function : allows up to 16 channels to be set • Low-power consumption modes • Sleep mode (CPU operation clock stops) • Timebase timer mode (oscillation clock and timebase timer operate) • Stop mode (oscillation clock stops) • CPU intermittent operation mode (CPU operates intermittently at the specified intervals) • Package • QFP-100 (FPT-100P-M06 : 0.65 mm pin pitch) • Process • CMOS technology • I/O ports : Maximum 26 (26 ports, also used for internal resources) • Timebase timer : 1 channel • Watchdog timer : 1 channel • 16-bit reload timer : 3 channels • 16-bit freerun timers : 1 channel • Output compare : 1 channel • If the count value of the 16-bit freerun timer and compare register setting match, an interrupt request can be output • Input capture : 2 channels • By detecting a valid edge in a signal input from the external input pin, it is possible to read the 16-bit freerun timer count into the input capture data register, and output an interrupt request. • Serial I/O : 2 channels • UART : 2 channels • Includes full-duplex double buffer (8 bits length) • Can be set to clock-asynchronous transfer or clock-synchronized serial transfer (I/O extended serial) • DTP/external interrupt (4 channels) • Extended intelligent I/O service can be started via external input • It is possible to generate an internal hardware interrupt via external input • Delayed interrupt generation module • It is possible to output task switching interrupt requests • 8/10 bit A/D converter (16 channels) • Choice of 8 and 10-bit resolution selectable (Continued) |
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