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MB90F372 Datasheet(PDF) 2 Page - Fujitsu Component Limited. |
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MB90F372 Datasheet(HTML) 2 Page - Fujitsu Component Limited. |
2 / 140 page MB90370/375 Series 2 (Continued) While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90370/375 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which enables processing of long-word data. *1 : F2MC stands for FUJITSU Flexible Microcontroller and a registered trademark of FUJITSU LIMITED. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. s s s s FEATURES • Clock • Embedded PLL clock multiplication circuit • Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz to 16 MHz) . • Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at VCC of 3.3 V) • CPU addressing space of 16M bytes • Internal 24-bit addressing • Instruction set optimized for controller applications • Rich data types (bit, byte, word, long word) • Rich addressing mode (23 types) • High code efficiency • Enhanced precision calculation realized by the 32-bit accumulator • Instruction set designed for high level language (C) and multi-task operations • Adoption of system stack pointer • Enhanced pointer indirect instructions • Barrel shift instructions • Program patch function (2 address pointer) • Improved execution speed • 4-byte instruction queue • Powerful interrupt function • Priority level programmable : 8 levels • 32 factors of stronger interrupt function • Automatic data transmission function independent of CPU operation • Extended intelligent I/O service function (EI2OS) • Maximum 16 channels • Low-power consumption (standby) mode • Sleep mode (mode in which CPU operating clock is stopped) • Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped) • Stop mode (mode in which all oscillations are stopped) • CPU intermittent operation mode • Watch mode • Package • LQFP-144 (FPT-144P-M12 : 0.4 mm pitch) • Process •CMOS technology |
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