BS616LV1010TCG70 datasheet(4/11 Pages) BSI

Part #	BS616LV1010TCG70

Description	Very Low Power CMOS SRAM 1M X 16 bit

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Manufacturer	BSI [Brilliance Semiconductor]

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BS616LV1611

R0201-BS616LV1611

Revision

2.3

May.

2006

4

n DATA RETENTION CHARACTERISTICS (T

A = -40

OC to +85OC)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.

(1)

MAX.

UNITS

VDR

VCC for Data Retention

CE1≧VCC-0.2V or CE2≦0.2V,

VIN≧VCC-0.2V or VIN≦0.2V

1.5

--

V

ICCDR

(3)

Data Retention Current

CE1≧VCC-0.2V or CE2≦0.2V,

VIN≧VCC-0.2V or VIN≦0.2V

--

0.8

8.0

uA

tCDR

Chip Deselect to Data

Retention Time

0

--

ns

tR

Operation Recovery Time

See Retention Waveform

tRC

(2)

--

ns

1. VCC=1.5V, TA=25

OC and not 100% tested.

2. tRC = Read Cycle Time.

3. ICCDR(Max.) is 6.0uA at TA=70

OC.

n LOW V

CC DATA RETENTION WAVEFORM (1) (CE1 Controlled)

n LOW V

CC DATA RETENTION WAVEFORM (2) (CE2 Controlled)

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output Timing

Reference Level

0.5Vcc

tCLZ, tOLZ, tCHZ, tOHZ, tWHZ

CL = 5pF+1TTL

Output Load

Others

CL = 30pF+1TTL

1. Including jig and scope capacitance.

n KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE

STEADY

MUST BE

STEADY

MAY CHANGE

FROM

“H” TO “L”

WILL BE CHANGE

FROM

“H” TO “L”

MAY CHANGE

FROM

“L” TO “H”

WILL BE CHANGE

FROM

“L” TO “H”

DON

’T CARE

ANY CHANGE

PERMITTED

CHANGE :

STATE UNKNOW

DOES NOT

APPLY

CENTER LINE IS

HIGH INPEDANCE

“OFF” STATE

CE2

Data Retention Mode

VCC

tCDR

VCC

tR

VIL

VCC

VDR≧1.5V

CE2≦0.2V

Data Retention Mode

VCC

tCDR

VCC

tR

VIH

CE1≧VCC - 0.2V

VDR≧1.5V

CE1

VCC

CL

(1)

1 TTL

Output

ALL INPUT PULSES

→ ←

90%

VCC

GND

Rise Time:

1V/ns

Fall Time:

1V/ns

90%

→ ←

10%

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BS616LV1010TCG70 Datasheet(PDF) 4 Page - Brilliance Semiconductor

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