BS616UV4016

R0201-BS616UV4016

Revision

1.6

May.

2006

8

WRITE CYCLE 2

(1,6)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All

signals must be active to initiate a write and any one signal can terminate a write by going

inactive. The data input setup and hold timing should be referenced to the second transition

edge of the signal that terminates the write.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals

of opposite phase to the outputs must not be applied to them.

10.Transition is measured

± 500mV from steady state with C

The parameter is guaranteed but not 100% tested.

12.The change of Read/Write cycle must accompany with CE or address toggled.

(11)

(2)

(4,10)

(3)

WE

LB, UB

CE

ADDRESS

(5)

(7)

(8)

(8,9)

(12)