BH616UV1611

R0201-BH616UV1611

Revision

1.3

Otc.

2006

2

n PIN DESCRIPTIONS

Name

Function

A0 to A20 Address Input (byte mode)

(TSOP only)

These 21 address inputs select one of the 2,048K x 8 bit in the RAM, If BYTE is LOW

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in standby power mode. The DQ pins will be in the high impedance

state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impendence state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

BYTE Byte Enable Input (TSOP only)

This input selects the organization of the SRAM. 1,024K x 16-bit configuration is

selected if BYTE is HIGH. 2,048K x 8-bit configuration is selected if BYTE is LOW

DQ0-DQ15 Data Input/Output

Ports

16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground