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STM32F103C8T6 Datasheet(PDF) 66 Page - STMicroelectronics |
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STM32F103C8T6 Datasheet(HTML) 66 Page - STMicroelectronics |
66 / 67 page Revision history STM32F103xx 66/67 8 Revision history Table 48. Document revision history Date Revision Changes 01-jun-2007 1 Initial release. 20-Jul-2007 2 Flash memory size modified in Note 5, Note 4, Note 6, Note 7 and BGA100 pins added to Table 3: Pin definitions. Figure 5: STM32F103xx performance line BGA100 ballout added. THSE changed to TLSE in Figure 12: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes. tSU(LSE) changed to tSU(HSE) in Table 17: HSE 4-16 MHz oscillator characteristics. IDD(HSI) max value added to Table 19: HSI oscillator characteristics. Sample size modified and machine model removed in Electrostatic discharge (ESD). Number of parts modified and standard reference updated in Static latch-up. 25 °C and 85 °C conditions removed and class name modified in Table 28: Electrical sensitivities. RPU and RPD min and max values added to Table 29: I/O static characteristics. RPU min and max values added to Table 32: NRST pin characteristics. Figure 18: I2C bus AC waveforms and measurement circuit and Figure 17: Recommended NRST pin protection corrected. Notes removed below Table 7, Table 32, Table 37. IDD typical values changed in Table 11: Maximum current consumption in Run and Sleep modes. Table 33: TIMx characteristics modified. tSTAB, VREF+ value, tlat and fTRIG added to Table 39: ADC characteristics. In Table 24: Flash memory endurance and data retention, typical endurance and data retention for TA = 85 °C added, data retention for TA = 25 °C removed. VBG changed to VREFINT in Table 10: Embedded internal reference voltage. Document title changed. Controller area network (CAN) section modified. Figure 9: Power supply scheme modified. Features on page 1 list optimized. Small text changes. |
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