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CDB42L51 Datasheet(PDF) 10 Page - Cirrus Logic |
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CDB42L51 Datasheet(HTML) 10 Page - Cirrus Logic |
10 / 88 page 10 DS679F1 CS42L51 2. TYPICAL CONNECTION DIAGRAMS 1 µF +1.8 V or +2.5 V 1 µF VQ DAC_FILT+ 0.1 µF 1 µF DGND VL 0.1 µF +1.8 V, +2.5 V or +3.3 V SCL/CCLK SDA/CDIN RESET 2 k Ω See Note 1 LRCK AGND AD0/CS MCLK SCLK 0.1 µF VA_HP VD * Capacitors must be C0G or equivalent 150 pF AFILTA AFILTB MICIN1 AIN3A Microphone Input 150 pF SDIN SDOUT CS42L51 2 k Ω 1 µF BIAS2 AIN3B/MICIN2 ** +1.8 V or +2.5 V AOUTB AOUTA 470 Ω 470 Ω C C Rext Rext See Note 2 AIN1A Left Analog Input 1 1800 pF 1800 pF 100 k Ω 100 Ω AIN1B Right Analog Input 1 * * Note 1: Resistors are required for I²C control port operation For best response to Fs/2 : () 470 4 470 × + = ext ext R Fs R C π This circuitry is intended for applications where the CS42L51 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. Note 2 : RL See Note 3 Note 3: The value of RL is dictated by the microphone cartridge. Digital Audio Processor 0.1 µF VA Headphone Out Left & Right Line Level Out Left & Right Speaker Driver AIN2A Left Analog Input 2 1800 pF 1800 pF AIN2B BIAS1 Right Analog Input 2 * * FLYP FLYN VSS_HP GND_HP 1 µF 10 µF ADC_FILT+ Microphone Bias 1 µF 1 µF 1 µF 1 µF 1 µF 0.1 µF 51.1 Ω 0.022 µF 100 k Ω 100 Ω 100 Ω 100 Ω 100 k Ω 100 k Ω 100 k Ω 1 µF ** ** * *Use low ESR ceramic capacitors. See Note 4 Note 4: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . 1.5 µF 1.5 µF See Note 5 Note 5 : Larger capacitors, such as 1.5 µF, improves the charge pump performance (and subsequent THD +N) at the full scale output power achieved with gain (G) settings greater than default. ** ** Figure 1. Typical Connection Diagram (Software Mode) |
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