Low-Jitter, Precision Clock Generator

with Four Outputs

6

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Pin Description

PIN

NAME

FUNCTION

1

Power Supply for QB0 and QB1 Clock Outputs. Connect to +3.3V.

2, 19, 24

GND

Supply Ground

3

QB0_OE

LVCMOS/LVTTL Input. Enables/disables QB0 clock output. Connect pin high or leave open to enable

LVPECL clock output QB0. Connect low to set QB0 to a logic 0. Has internal 50k

input impedance.

4, 5

SELB1,

SELB0

LVCMOS/LVTTL Input. Controls NB divider setting. Has 50k

input impedance. See Table 2 for

more information.

6

QAC_OE

LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high or leave open to enable

QA_C. Connect low to set QA_C to a high-impedance state. Has internal 75k

7

MR

LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal

75k

pulldown to GND. Not required for normal operation.

8

GNDO_A

Ground for QA_C Output. Connect to supply ground.

9

QA_C

LVCMOS Clock Output

10

Power Supply for QA_C Clock Output. Connect to +3.3V.

11

Power Supply for QA Clock Output. Connect to +3.3V.

12

QA

Noninverting Clock Output, LVPECL

13

QA

Inverting Clock Output, LVPECL

14

BYPASS

LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high or leave

open for normal operation. When in bypass mode the output dividers are set to divide by 1. Has

internal 75k

15, 16

FB_SEL1,

FB_SEL0

LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal

75k

pulldown to GND.

17

Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering,

18

Core Power Supply. Connect to +3.3V.

20

QA_OE

LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high or leave open to

enable the LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k

21, 22

SELA0,

SELA1

LVCMOS/LVTTL Input. Controls NA divider setting. See Table 2 for more information. Has 50k

input impedance.

23

QB1_OE

LVCMOS/LVTTL Input. Enables/disables QB1 clock output. Connect pin high or leave open to enable

LVPECL clock output QB1. Connect low to set QB1 to a logic 0. Has internal 50k

input impedance.

25

X_OUT

Crystal Oscillator Output

26

X_IN

Crystal Oscillator Input

27

REF_IN

LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling.

28

IN_SEL

LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN.

Has internal 75k

29

QB1

LVPECL, Inverting Clock Output

30

QB1

LVPECL, Noninverting Clock Output

31

QB0

LVPECL, Inverting Clock Output

32

QB0

LVPECL, Noninverting Clock Output

—

EP

Exposed Pad. Connect to supply ground for proper electrical and thermal performance.