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ATTINY26L-8MI Datasheet(PDF) 10 Page - ATMEL Corporation |
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ATTINY26L-8MI Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 19 page 10 ATtiny26(L) 1477J–AVR–06/07 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-inc. Rd ← (Z), Z ← Z + 1 None 2 LD Rd, -Z Load Indirect and Pre-dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-inc. (X) ← Rr, X ← X + 1 None 2 ST -X, Rr Store Indirect and Pre-dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-inc. (Y) ← Rr, Y ← Y + 1 None 2 ST -Y, Rr Store Indirect and Pre-dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q, Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 IN Rd, P In Port Rd ← PNone 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register I/O(P,b) ← 1None 2 CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Z,C,N,V 1 ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit Load from T to Register Rd(b) ← TNone 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Zero Flag Z ← 0Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0S 1 SEV Set Two’s Complement Overflow V ← 1V 1 CLV Clear Two’s Complement Overflow V ← 0V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0T 1 SEH Set Half-carry Flag in SREG H ← 1H 1 CLH Clear Half-carry Flag in SREG H ← 0H 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks |
Similar Part No. - ATTINY26L-8MI |
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Similar Description - ATTINY26L-8MI |
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