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CX20470 Datasheet(PDF) 4 Page - Skyworks Solutions Inc. |
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CX20470 Datasheet(HTML) 4 Page - Skyworks Solutions Inc. |
4 / 18 page CX20470 CDMA BAP 4 Skyworks – Preliminary 101106A Proprietary Information and Specifications are Subject to Change August 24, 2000 Technical Description The CX20470 consists of a CDMA transmit and receive path, FM transmit and receive path, Intermediate Frequency (IF) PLL synthesizer section, an auxiliary control section, and an audio CODEC section. Each of these functional sections is detailed in the complete CX20470 system block diagram shown in Figure 4. CDMA Transmit Path The CDMA transfer signal path accepts two different interface formats from the baseband ASIC: analog signal and digital data. The interface format configuration can be controlled through BAP control register. For analog signal interface, the BAP accepts I and Q analog transmit signals from the digital modem and performs transmit low- pass filters with a bandwidth of 1 MHz for image rejection. The I and Q filtered signals are then output to the transmitter. For digital signal interface, the BAP transmit signal path accepts digital I and Q data baseband signals form the baseband modem and outputs analog I and Q components to the IF transmitter. Eight bits of I and Q transmit data are input to the CDMA Digital-to- Analog Converters (DACs) by multiplexing over and 8-bit input port on the BAP. At the falling edge of the transmit clock input (TxCLK/), the 8-bit parallel transmit data is registered into I DAC, and, at the rising edge, registered into Q DAC. The outputs from I DAC and Q DAC are followed by transmit low-pass reconstruction filters with a bandwidth of 630 kHz for removal of unwanted frequency components. The precise I and Q signals are output to the transmitter. CDMA Receive Path The BAP receive path is designed to accept I and Q baseband analog components. These signals are input into lowpass filters specifically designed for CDMA. These filters, when combined with the external IF bandpass filtering, provide the necessary receiver passband, rejection band amplitude, and phase response. The control of DC offset is made to the I and Q signals from the inputs IOFFSET and QOFFSET. Analog voltages at these inputs adjust the offset before the A/D conversion. Two identical 4-bit flash ADCs sample the I and Q signals at a rate of 9.8304 MHz (CHIPx8) and output the four bits each in parallel to a baseband device. FM Transmit Path The FM transmit signal path accepts two different interface formats from the baseband ASIC: analog signal and digital data. The interface format configuration can be controlled through BAP control register. For the analog signal interface, the BAP accepts I and Q analog signals from the digital modem and perform transmit low-pass filters. The I and Q transmit filters are then output to the transmitter. For the digital signal interface, the FM modulation signal is created from an 8-bit DAC, which is the Q signal DAC re-used from the CDMA section. The DAC rate is determined from the transmit clock input (TXCLK/) and the digital input is 8-bit parallel. The DAC analog output is the analog output FM modulation signal used to directly control a transmit VCO using external components. FM Receive Path The receive path for FM operation is similar to that for CDMA operation. The differences are that the receive path uses 15 kHz bandwidth low-pass filters and provides 8-bit serial output ADCs. These ADCs sample the analog I and Q signals at a rate determined by the strobe (RXFMSTB). The digital data is output serially and determined by the FMCLK beginning with the Most Significant Bit (MSB) of the result. IF PLL Synthesizer Section Two identical and independent PLL synthesizers are provided to synthesize the transmit and receive IF frequencies. Each contains a dual modulus divide by 16/17 prescaler, a 13-bit R counter, a 17- bit N counter, a phase detector, and a charge pump current and lock detector configuration. The synthesizers accept differential VCO inputs up to 640 MHz and a shared TCXO reference input. CDMA Auxiliary Section The auxiliary section of the CDMA BAP includes mode control logic, a general purpose ADC, and clock generation. Mode Control Logic. The BAP has several operating modes, each one selected by one of three digital inputs: FM, IDLE, and SLEEP. • CDMA RxTx or FM RxTx mode: When a call is in progress. • IDLE mode: When a call is not in progress but the telephone is ready to answer a call. • SLEEP mode (low-power mode): Calls cannot be received but the digital processor and keypad are enabled. • CDMA slotted paging mode: IDLE mode only for paging slot, other time SLEEP mode. • Power-down mode: Device is in standby mode (leakage current consumption only). General Purpose ADC. The BAP provides an 8-bit resolution ADC that can be applied to monitor battery level, temperature, and/or sensors. Clock Generation. The CDMA BAP provides a digital and/or PLL clock synthesis network to generate TCXO/4 and CHIPx8 signals from a 19.2 MHz, 19.68 MHz, or 19.8 MHz system clock. The clock generation configuration can be programmed via the synthesizer’s three-wire serial interface. |
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