MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12015-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

CU,CV,CW

GND(Logic)

ASIPM

CPU

10k

Ω

5.1k

Ω

0.1nF

R

R

0.1nF

on

on

on

on

0

0

0

DC-Bus voltage

Control voltage supply

Boot-strap voltage

N-Side input signal

P-Side input signal

Brake input signal

b)

a)

PWM starts

N-side IGBT Current

N-side FWDi Current

t(hold)

td(read)

Delay time

on

off

on

off

0

0

on

off

0

Ref

V(hold)

Fig. 9 START-UP SEQUENCE

Normally at start-up, Fo and CL output signals will be pulled-up

Low (ON) level at the instant of the first ON input pulse to an N-Side

IGBT. This can happen particularly when the boot-strap capacitor is

charging sequence) is explained in the following graph

Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT

a) Boot-strap charging scheme :

Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20

µs number of pulses =10 ~ 500 de-

pending on the boot-strap capacitor size)

Apply ON signals to the following input pins : Br

→ Un/Vn/Wn → Up/Vp/Wp in that order.

Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.