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MAX4733 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX4733 Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 14 page Analog Signal Levels Analog signals that range over the entire supply voltage (GND to V+) pass with very little change in RON (see Typical Operating Characteristics). The bidirectional switches allow NO_, NC_, and COM_ connections to be used as either inputs or outputs. Power-Supply Sequencing and Overvoltage Protection CAUTION: Do not exceed the absolute maximum ratings. Stresses beyond the listed ratings can cause permanent damage to the devices. Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+ before applying analog signals, especially if the analog signal is not current limited. If this sequencing is not possible, and if the analog inputs are not current limited to < 20mA, add a small-signal diode, D1, as shown in Figure 1. If the analog signal can dip below GND, add D2. Adding protection diodes reduces the analog signal range to a diode drop (about 0.7V) below V+ (for D1), and to a diode drop above ground (for D2). Leakage is unaffect- ed by adding the diodes. On-resistance increases slightly at low supply voltages. Maximum supply volt- age (V+) must not exceed +11V. Adding protection diodes causes the logic thresholds to be shifted relative to the power-supply rails. The most significant shift occurs when using low supply voltages (+5V or less). With a +5V supply, TTL compatibility is not guaranteed when protection diodes are added. Driving IN1 and IN2 all the way to the supply rails (i.e., to a diode drop higher than the V+ pin, or to a diode drop lower than the GND pin) is always acceptable. Protection diodes D1 and D2 also protect against some overvoltage situations. Using the circuit in Figure 1, no damage results if the supply voltage is below the absolute maximum rating (+12V) and if a fault voltage up to the absolute maximum rating (V+ + 0.3V) is applied to an analog signal terminal. UCSP Applications Information For the latest application details on USCP construction, dimensions, tape carrier information, printed circuit board techniques, bump-pad layout, and recommend- ed reflow temperature profile as well as the latest infor- mation on reliability testing results, go to the Maxim web site at www.maxim-ic.com/ucsp to find the Application Note: UCSP—A Wafer-Level Chip-Scale Package. 50 Ω, Dual SPST Analog Switches in UCSP 8 _______________________________________________________________________________________ MAX4731 MAX4732 MAX4733 NO_ COM_ GND V+ *INTERNAL PROTECTION DIODES. D2 D1 EXTERNAL BLOCKING DIODE EXTERNAL BLOCKING DIODE GND V+ * * * * Figure 1. Overvoltage Protection Using External Blocking Diodes Test Circuits/Timing Diagrams |
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