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ICS85454AK-01 Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS85454AK-01 Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 15 page 85454AK-01 www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2006 5 Integrated Circuit Systems, Inc. ICS85454-01 DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER ADDITIVE PHASE JITTER Additive Phase Jitter at 622.08MHz (12kHz - 20MHz) = 0.05ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a As with most timing specifications, phase noise measure- ments have issues. The primary issue relates to the limita- tions of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated ratio of the power in the 1Hz band to the power in the funda- mental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the fre- quency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) |
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