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CYV15G0404RB
Document #: 38-02102 Rev. *C
Page 4 of 27
Reclocking Deserializer Path Block Diagram (continued)
=
Internal Signal
INC1+
INC1–
INC2+
INC2–
INSELC
Clock &
Data
Recovery
PLL
LFIC
10
RXDC[9:0]
Receive
Signal
Monitor
RXCLKC+
RXCLKC–
÷2
RXPLLPDC
SPDSELC
ULCC
RXRATEC
10
10
RXBISTC[1:0]
LDTDEN
SDASEL[2..1]C[1:0]
ROUTC1+
ROUTC1–
ROUTC2+
ROUTC2–
ROE[2..1]C
TRGCLKC
x2
TRGRATEC
BISTSTC
Character-Rate Clock C
Reclocker
RECLKOC
Recovered Character Clock
Recovered Serial Data
REPDOC
Clock Multiplier C
Output PLL
ROE[2..1]C
IND1+
IND1–
IND2+
IND2–
INSELD
Clock &
Data
Recovery
PLL
LFID
10
RXDD[9:0]
Receive
Signal
Monitor
RXCLKD+
RXCLKD–
÷2
RXPLLPDD
SPDSELD
ULCD
RXRATED
10
10
RXBISTD[1:0]
LDTDEN
SDASEL[2..1]D[1:0]
ROUTD1+
ROUTD1–
ROUTD2+
ROUTD2–
ROE[2..1]D
TRGCLKD
x2
TRGRATED
BISTSTD
Character-Rate Clock D
Reclocker
RECLKOD
Recovered Character Clock
Recovered Serial Data
REPDOD
Clock Multiplier D
Output PLL
ROE[2..1]D
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