CYRF69213
Document #: 001-07552 Rev. *B
Page 3 of 85
Pinout
Pin
Name
Function
1
P0.4
Individually configured GPIO
2
Xtal_in
12 MHz Crystal. External Clock in
3, 7, 16
VCC
Connected to pin 24 via 0.047-
µF Capacitor.
4
P0.3
Individually configured GPIO
5
P0.1
Individually configured GPIO
6, 9, 39
Vbat
Connected to pin 24 via 0.047-
µFshunt capacitor
8
P2.1
GPIO. Port 2 Bit 1
10
RF Bias
RF pin voltage reference
11
RFp
Differential RF input to/from antenna
12
GND
Ground
13
RFn
Differential RF to/from antenna
14, 17, 18, 20,
36
NC
15
P2.0
GPIO. Port 2 Bit 0
19
RESV
Reserved. Must connect to GND
21
D+
Low-speed USB IO
22
D–
Low-speed USB IO
23
VDD_micro
4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU
24
P1.2 / VREG
Must be configured as 3.3V output. It must have a 1–2
µF output capacitor
25
P1.3 / nSS
Slave select SPI Pin
26
P1.4 / SCK
Serial Clock Pin from MCU function to radio function
27
IRQ
Interrupt output, configure high/low or GPIO
28
P1.5 / MOSI
Master Out Slave In.
29
MISO
Master In Slave Out, from radio function.Can be configured as GPIO
30
XOUT
Bufferd CLK, PACTL_n or GPIO
31
PACTL
Control for external PA or GPIO
32
P1.6
GPIO. Port 1 Bit 6
33
VIO
I/O interface voltage. Connected to pin 24 via 0.047
µF
34
Reset
Radio Reset. Connected to VDD via 0.47 µF Capacitor or to microcontroller GPIO pin. Must
have a RESET = HIGH event the very first time power is applied to the radio otherwise the
state of the radio function control registers is unknown.
35
P1.7
GPIO. Port 1 Bit 7
36
VDD_1.8
Regulated logic bypass. Connected via 0.47
µF to GND
37
L/D
Connected to GND
38
P0.7
GPIO. Port 0 Bit 7
40
Vreg
Connected to pin 24
41
E-pad
Connected to GND
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