Document #: 38-06069 Rev. *I
Page 9 of 25
CYD04S72V
CYD09S72V
CYD18S72V
IEEE 1149.1 Serial Boundary Scan (JTAG)[20]
The FLEx72 incorporates an IEEE 1149.1 serial boundary
scan test access port (TAP). The TAP controller functions in a
manner that does not conflict with the operation of other
devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
FLEx72 family and may be performed while the device is
operating. An MRST must be performed on the FLEx72 after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the FLEx72 in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
Boundary Scan Hierarchy for FLEx72 Family
Internally, the CYD04S72V and CYD09S72V have two DIEs
while CYD18S72V have four DIEs. Each DIE contains all the
circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain
of each DIE is connected serially to form the scan chain of the
FLEx72 family as shown in Figure 3. TMS and TCK are
connected in parallel to each DIE to drive all 4 TAP controllers
in unison. In many cases, each DIE will be supplied with the
same instruction. In other cases, it might be useful to supply
different instructions to each DIE. One example would be
testing the device ID of one DIE while bypassing the others.
Each pin of FLEx72 family is typically connected to multiple
DIEs. For connectivity testing with the EXTEST instruction, it
is desirable to check the internal connections between DIEs
as well as the external connections to the package. This can
be accomplished by merging the netlist of the devices with the
netlist of the user’s circuit board. To facilitate boundary scan
testing of the devices, Cypress provides the BSDL file for each
DIE, the internal netlist of the device, and a description of the
device scan chain. The user can use these materials to easily
integrate the devices into the board’s boundary scan
environment. Further information can be found in the Cypress
application note Using JTAG Boundary Scan For System In a
Package (SIP) Dual-Port SRAMs.
Notes:
19. The “X” in this diagram represents the counter upper bits.
20. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
216 215
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22
24 23
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216 215
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21
25
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24 23
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216 215
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24 23
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216 215
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24 23
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H
H
L
H
11
0s
1
0
1
0
1
01
00
Xs
1
X
0
X
0
X0
11
Xs
1
X
1
X
1
X1
00
Xs
1
X
0
X
0
X0
Masked Address
Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation[1, 19]
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