CY62157EV18 MoBL®
Document #: 38-05490 Rev. *D
Page 5 of 12
Switching Characteristics (Over the Operating Range) [11, 12]
Parameter
Description
55 ns
Unit
Min
Max
Read Cycle
tRC
Read Cycle Time
55
ns
tAA
Address to Data Valid
55
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
55
ns
tDOE
OE LOW to Data Valid
25
ns
tLZOE
5ns
tHZOE
18
ns
tLZCE
CE1 LOW and CE2 HIGH to Low-Z [13]
10
ns
tHZCE
18
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
0
ns
tPD
CE1 HIGH and CE2 LOW to Power Down
55
ns
tDBE
BLE/BHE LOW to Data Valid
55
ns
BLE/BHE LOW to Low-Z [13]
10
ns
tHZBE
18
ns
tWC
Write Cycle Time
45
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
18
ns
tLZWE
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
