Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-08030 Rev. *E
Revised August 01, 2007
CY62137FV18 MoBL®
2-Mbit (128K x 16) Static RAM
Features
■ Very high speed: 55 ns
■ Wide voltage range: 1.65V–2.25V
■ Pin compatible with CY62137CV18
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 5 µA
■ Ultra low active power
❐ Typical active current: 1.6 mA @ f = 1 MHz
■ Ultra low standby power
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Byte power down feature
■ Available in a Pb-free 48-Ball VFBGA package
Functional Description
The CY62137FV18 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO0 through IO15) are placed
in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both the Byte High Enable and the Byte Low Enable are
disabled (BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from the memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
128K x 16
RAM Array
IO0–IO7
A8
A7
A6
A5
A2
COLUMN DECODER
DATA IN DRIVERS
OE
A4
A3
IO8–IO15
CE
WE
BHE
A0
A1
A9
A10
BLE
BHE
BLE
CE
POWER DOWN
CIRCUIT
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
