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PRELIMINARY
CY7C1522AV18
CY7C1529AV18
CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 3 of 28
Selection Guide
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
900
860
800
700
650
mA
Logic Block Diagram (CY7C1523AV18)
2M x 18
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
LD
Q[17:0]
Control
Logic
Reg.
Reg.
Reg.
18
18
36
Write
18
BWS0
VREF
Data Reg
Write
Data Reg
Memory
Array
2M x 18
Memory
Array
18
18
21
18
C
C
BWS1
R/W
LD
R/W
CQ
CQ
DOFF
Logic Block Diagram (CY7C1524AV18)
1M x 36
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
LD
Q[35:0]
Control
Logic
Reg.
Reg.
Reg.
36
36
72
Write
36
BWS[3:0]
VREF
Data Reg
Write
Data Reg
Memory
Array
1M x 36
Memory
Array
36
36
20
36
C
C
R/W
LD
R/W
CQ
CQ
DOFF
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