CY14B104L/CY14B104N
PRELIMINARY
Document #: 001-07102 Rev. *E
Page 4 of 21
Device Operation
The CY14B104L/CY14B104N nvSRAM is made up of two
functional components paired in the same physical cell. They
are an SRAM memory cell and a nonvolatile QuantumTrap
cell. The SRAM memory cell operates as a standard fast static
RAM. Data in the SRAM can be transferred to the nonvolatile
cell (the STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique architecture
allows all cells to be stored and recalled in parallel.During the
STORE and RECALL operations SRAM read and write
operations
are
inhibited.
The
CY14B104L/CY14B104N
suports infinite reads and writes just like a typical SRAM.In
addition,it provides infinite RECALL operations from the
nonvolatile cells and up to 200K STORE operations.
SRAM Read
The CY14B104L/CY14B104N performs a READ cycle
whenever CE and OE are LOW while WE and HSB are HIGH.
The address specified on pins A0-18/A0-17 determines which of
the 524,288 data bytes or 262,144 words of 16 bits each will
be accessed. When the read is initiated by an address
transition, the outputs will be valid after a delay of tAA (read
cycle #1). If the read is initiated by CE or OE, the outputs will
be valid at tACE or at tDOE, whichever is later (read cycle #2).
The data outputs will repeatedly respond to address changes
within the tAA access time without the need for transitions on
any control input pins, and will remain valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common IO pins DQ0–15 will be written into the memory if the
data is valid tSD before the end of a WE controlled WRITE or
before the end of an CE controlled WRITE. It is recommended
that OE kept high during the entire WRITE cycle to avoid data
bus contention on common IO lines. If OE is left low, internal
circuitry turns off the output buffers tHZWE after WE goes low.
AutoStore Operation
The CY14B104L/CY14B104N stores data to nvSRAM using
one of the three storage operations. These three operations
are Hardware Store activated by HSB, Software Store
activated by an address sequence, and AutoStore on device
power down. AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104L/CY14B104N.
During normal operation, the device draws current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC. A
STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 1shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC
Electrical Characteristics on page 8 for the size of VCAP.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. Monitor the HSB signal by the system to detect if
an AutoStore cycle is in progress.
Figure 1. AutoStore Mode
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB pin for
controlling and acknowledging the STORE operations. Use
the HSB pin to request a hardware STORE cycle. When the
HSB pin is driven low, the CY14B104L/CY14B104N condi-
tionally initiates a STORE operation after tDELAY. An actual
STORE cycle only begins if a WRITE to the SRAM took place
since the last STORE or RECALL cycle. The HSB pin also acts
as an open drain driver that is internally driven low to indicate
a busy condition while the STORE (initiated by any means) is
in progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B104L/CY14B104N continues SRAM
operations for tDELAY. During tDELAY, multiple SRAM READ
operations may take place. If a WRITE is in progress when
HSB is pulled low it will be allowed a time, tDELAY to complete.
However, any SRAM WRITE cycles requested after HSB goes
low will be inhibited until HSB returns high.
During any STORE operation, regardless of how it was
initiated, the CY14B104L/CY14B104N continues to drive the
HSB pin low, releasing it only when the STORE is complete.
V
CC
V
CC
V
CAP
WE
V
CC
V
CC
V
CAP
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