PRELIMINARY
CY14B256L
Document #: 001-06422 Rev. *E
Page 10 of 17
AutoStore/Power Up RECALL
Parameter
Description
CY14B256L
Unit
Min
Max
tHRECALL [12]
Power Up RECALL Duration
20
ms
tSTORE [13, 14]
STORE Cycle Duration
12.5
ms
VSWITCH
Low Voltage Trigger Level
2.65
V
tVCCRISE
VCC Rise Time
150
µs
Software Controlled STORE/RECALL Cycle [15, 16]
Parameter
Description
25 ns part
35 ns part
45 ns part
Unit
Min
Max
Min
Max
Min
Max
tRC
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tAS
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
20
25
30
ns
tGHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
50
50
50
µs
tSS[17, 18]
Soft Sequence Processing Time
70
70
70
µs
Hardware STORE Cycle
Parameter
Description
CY14B256L
Unit
Min
Max
tDELAY [19]
Time allowed to complete SRAM Cycle
1
70
µs
tHLHX
Hardware STORE Pulse Width
15
ns
Notes
11. If WE is low when CE goes low, the outputs remain in the high impedance state.
12. tHRECALL starts from the time VCC rises above VSWITCH.
13. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place.
14. Industrial grade devices require 15 ms max.
15. The software sequence is clocked with CE-controlled or OE-controlled READs.
16. The six consecutive addresses must be read in the order listed in the Table 1,Mode Selection, on page 5. WE must be HIGH during all six consecutive cycles.
17. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register the command.
18. Commands like STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
19. READ and WRITE cycles in progress before HSB are given this amount of time to complete.
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