February 15, 2007
Document No. 38-12013 Rev. *H
10
CY8C29x66 Final Data Sheet
1. Pin Information
1.1.3
48-Pin Part Pinouts
Table 1-3. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Pin
Name
Description
CY8C29666 48-Pin PSoC Device
Digital
Analog
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
5
IO
P2[7]
6
IO
P2[5]
7
IO
I
P2[3]
Direct switched capacitor block input.
8
IO
I
P2[1]
Direct switched capacitor block input.
9
IO
P4[7]
10
IO
P4[5]
11
IO
P4[3]
12
IO
P4[1]
13
Power
SMP
Switch Mode Pump (SMP) connection to
external components required.
14
IO
P3[7]
15
IO
P3[5]
16
IO
P3[3]
17
IO
P3[1]
18
IO
P5[3]
19
IO
P5[1]
20
IO
P1[7]
I2C Serial Clock (SCL).
21
IO
P1[5]
I2C Serial Data (SDA).
22
IO
P1[3]
23
IO
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
24
Power
Vss
Ground connection.
25
IO
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
26
IO
P1[2]
27
IO
P1[4]
Optional External Clock Input (EXTCLK).
28
IO
P1[6]
29
IO
P5[0]
30
IO
P5[2]
31
IO
P3[0]
32
IO
P3[2]
33
IO
P3[4]
34
IO
P3[6]
35
Input
XRES
Active high external reset with internal pull
down.
36
IO
P4[0]
37
IO
P4[2]
38
IO
P4[4]
39
IO
P4[6]
40
IO
I
P2[0]
Direct switched capacitor block input.
41
IO
I
P2[2]
Direct switched capacitor block input.
42
IO
P2[4]
External Analog Ground (AGND).
43
IO
P2[6]
External Voltage Reference (VREF).
44
IO
I
P0[0]
Analog column mux input.
45
IO
IO
P0[2]
Analog column mux input and column output.
46
IO
IO
P0[4]
Analog column mux input and column output.
47
IO
I
P0[6]
Analog column mux input.
48
Power
Vdd
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
SSOP
A, I, P0[7]
Vdd
A, IO, P0[5]
P0[6], A, I
A, IO, P0[3]
P0[2], A, IO
A, I, P0[1]
P0[4], A, IO
P2[7]
P0[0], A, I
P2[5]
P2[6],ExternalVREF
A, I, P2[3]
P2[4],ExternalAGND
A, I, P2[1]
P2[2], A, I
P4[7]
P2[0], A, I
P4[5]
P4[6]
P4[3]
P4[4]
P4[1]
P4[2]
SMP
P4[0]
P3[7]
XRES
P3[5]
P3[6]
P3[3]
P3[4]
P3[1]
P3[2]
P5[3]
P3[0]
P5[1]
P5[2]
I2CSCL, P1[7]
P5[0]
I2CSDA, P1[5]
P1[6]
P1[3]
P1[4],EXTCLK
I2CSCL,XTALin,P1[1]
P1[2]
Vss
P1[0],XTALout,I2CSDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
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