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CY7C1510V18
CY7C1525V18
CY7C1512V18
CY7C1514V18
Document #: 38-05489 Rev. *D
Page 3 of 27
Logic Block Diagram (CY7C1512V18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
18
36
18
BWS[1:0]
VREF
18
A(20:0)
21
C
C
18
Write
Reg
Write
Reg
CQ
CQ
18
DOFF
Logic Block Diagram (CY7C1514V18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
36
72
36
BWS[3:0]
VREF
36
A(19:0)
20
C
C
36
Write
Reg
Write
Reg
CQ
CQ
36
DOFF
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