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CY7C1566V18-375BZI Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1566V18-375BZI
Description  72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1566V18-375BZI Datasheet(HTML) 9 Page - Cypress Semiconductor

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CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Document Number: 001-06551 Rev. *D
Page 9 of 27
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL is
disabled by applying ground to the DOFF pin. When the DLL is
turned off, the device behaves in DDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
the
application
note,
DLL
Considerations
in
QDRII/DDRII/QDRII+/DDRII+. The DLL is also reset by slowing
or stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock at the
desired frequency. During power up, when the DOFF is tied
HIGH, the DLL gets locked after 2048 cycles of stable clock.
Application Example
Figure 1. Application Example
Truth Table
The truth table for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows. [3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
L
D(A) at K(t + 1)
D(A+1) at K(t + 1)
Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycle;
read data on consecutive K and K rising edges.
L-H
L
H
Q(A) at K(t + 2)
Q(A+1) at K(t + 3)
NOP: No Operation
L-H
H
X
High Z
High Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
BUS
MASTER
(CPU or ASIC)
DQ
Addresses
Cycle Start
R/W
Source CLK
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
R = 250ohms
LD
R/W
DQ
A
SRAM#1
K
ZQ
CQ/CQ
K
R = 250ohms
LD
R/W
DQ
A
SRAM#2
K
ZQ
CQ/CQ
K
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging
symmetrically.


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