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PRELIMINARY
CY7C1422BV18
CY7C1429BV18
CY7C1423BV18
CY7C1424BV18
Document Number: 001-07035 Rev. *B
Page 3 of 28
Logic Block Diagram (CY7C1423BV18)
1M x 18
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
LD
Q[17:0]
Control
Logic
Reg.
Reg.
Reg.
18
18
36
Write
18
BWS0
VREF
Data Reg
Write
Data Reg
Memory
Array
1M x 18
Memory
Array
18
18
20
18
C
C
BWS1
R/W
LD
R/W
CQ
CQ
DOFF
Logic Block Diagram (CY7C1424BV18)
512K x 36
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
LD
Q[35:0]
Control
Logic
Reg.
Reg.
Reg.
36
36
72
Write
36
BWS[3:0]
VREF
Data Reg
Write
Data Reg
Memory
Array
152K x 36
Memory
Array
36
36
19
36
C
C
R/W
LD
R/W
CQ
CQ
DOFF
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