PRELIMINARY
CY7C1422BV18
CY7C1429BV18
CY7C1423BV18
CY7C1424BV18
Document Number: 001-07035 Rev. *B
Page 6 of 28
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data Input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
CY7C1422BV18
− D
[7:0]
CY7C1429BV18
− D
[8:0]
CY7C1423BV18
− D
[17:0]
CY7C1424BV18
− D
[35:0]
LD
Input-
Synchronous
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data (one period of bus activity).
NWS[1:0]
Input-
Synchronous
Nibble Write Select 0, 1
− active LOW (CY7C1422BV18 only). Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS[3:0]
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
− active LOW. Sampled on the rising edge of the K and K
clocks during Write operations. Used to select which byte is written into the device during the
current portion of the Write operations. Bytes not written remain unaltered.
CY7C1429BV18
− BWS
0 controls D[8:0].
CY7C1423BV18
− BWS
0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1424BV18
− BWS
0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations. Internally,
the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1422BV18, 4M x 9 (2 arrays
each of 2M x 9) for CY7C1429BV18, 2M x 18 (two arrays each of 1M x 18) for CY7C1423BV18
and 1M x 36 (2 arrays each of 512K x 36) for CY7C1424BV18. Therefore only 21 address inputs
are needed to access the entire memory array of CY7C1422BV18 and CY7C1429BV18, 20
address inputs for CY7C1423BV18, and 19 address inputs for CY7C1424BV18. These inputs
are ignored when the appropriate port is deselected.
Q[x:0]
Output-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When Read access is deselected, Q[x:0] are automatically
tri-stated.
CY7C1422BV18
− Q
[7:0]
CY7C1429BV18
− Q
[8:0]
CY7C1423BV18
− Q
[17:0]
CY7C1424BV18
− Q
[35:0]
R/W
Input-
Synchronous
Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up
and hold times around edge of K.
C
Output-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
Output-
Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
K
Input-
Clock
Positive Input Clock for Output Data. The rising edge of K is used to capture synchronous
inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
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