PRELIMINARY
CY7C1516AV18
CY7C1527AV18
CY7C1518AV18
CY7C1520AV18
Document #: 001-06982 Rev. *B
Page 9 of 28
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device will behave in DDR-I mode (with one
cycle latency and a longer access time). For information refer
to
the
application
note
“DLL
Considerations
in
QDRII™/DDRII”.
Notes:
2. The above application shows two DDR-II used.
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑represents rising edge.
4. Device will power-up deselected and the outputs in a tri-state condition.
5. On CY7C1518AV18 and CY7C1520AV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1516AV18, “A1” represents A +‘0’ and A2 represents A +‘1.’
6. “t” represents the cycle at which a Read/Write operation is started. t+1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Application Example[2]
Truth Table[3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write Cycle: Load address; wait one cycle; input write data on
consecutive K and K rising edges.
L-H
L
L
D(A1) at K(t + 1)
↑ D(A2) at K(t + 1) ↑
Read Cycle: Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
L-H
L
H
Q(A1) at C(t + 1)
↑ Q(A2) at C(t + 2) ↑
NOP: No Operation
L-H
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Burst Address Table (CY7C1518AV18, CY7C1520AV18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
LD#
Vterm = 0.75V
Vterm = 0.75V
CC#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
K
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50ohms
R = 250ohms
R = 250ohms
[+] Feedback
[+] Feedback
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