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August 31, 2004

© 2004 Integrated Device Technology, Inc.

DSC 5701

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

Features

◆

RC32300 32-bit Microprocessor

– Up to 150 MHz operation

– Enhanced MIPS-II Instruction Set Architecture (ISA)

– Cache prefetch instruction

– Conditional move instruction

– DSP instructions

– Supports big or little endian operation

– MMU with 32 page TLB

– 8kB Instruction Cache, 2-way set associative

– 2kB Data Cache, 2-way set associative

– Cache locking per line

– Programmable on a page basis to implement a write-through

no write allocate, write-through write allocate, or write-back

algorithms for cache management

– Compatible with a wide variety of operating systems

◆

Local Bus Interface

– Up to 75 MHz operation

– 26-bit address bus

– 32-bit data bus

– Direct control of local memory and peripherals

– Programmable system watch-dog timers

– Big or little endian support

◆

Interrupt Controller simplifies exception management

◆

Four general purpose 32-bit timer/counters

◆

Programmable I/O (PIO)

– Input/Output/Interrupt source

– Individually programmable

◆

SDRAM Controller (32-bit memory only)

– 4 banks, non-interleaved

– Up to 512MB total SDRAM memory supported

– Implements full, direct control of discrete, SODIMM, or DIMM

memories

– Supports 16Mb through 512Mb SDRAM device depths

– Automatic refresh generation

◆

Serial Peripheral Interface (SPI) master mode interface

◆

UART Interface

– Two 16550 compatible UARTs

– Baud rate support up to 1.5 Mb/s

– Modem control signals available on one channel

◆

Memory & Peripheral Controller

– 6 banks, up to 64MB per bank

– Supports 8-,16-, and 32-bit interfaces

– Supports Flash ROM, SRAM, dual-port memory, and

peripheral devices

– Supports external wait-state generation

– 8-bit boot PROM support

– Flexible I/O timing protocols

Block Diagram

Figure 1 RC32334 Block Diagram

Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.

Local

Memory/IO

Control

Interrupt Control

DMA Control

Dual UART

32-bit Timers

SPI Control

Programmable I/O

PCI Bridge

IDT

Peripheral

Bus

RISCore32300

Enhanced MIPS-II ISA

Integer CPU

RC5000

Compatible

CP0

32-page

TLB

EJTAG

In-Circuit Emulator Interface

2kB

2-set, Lockable

Data Cache

8kB

2-set

Lockable

Instr. Cache

IPBus

Bridge

SDRAM

Control

79RC32334—Rev. Y

Communications Processor