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August 31, 2004

IDT 79RC32334—Rev. Y

mem_we_n[3:0]

Output

H

High

Memory Write Enable Negated Bus

Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and

mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.

mem_wait_n

Input

—

Memory Wait Negated

Requires external pull-up.

SRAM/IOI/IOM modes: Allows external wait-states to be injected during last cycle before data is sampled.

DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction.

Alternate function: sdram_wait_n.

mem_245_oe_n

Output

H

Low

Memory FCT245 Output Enable Negated

Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to

a memory or I/O bank.

mem_245_dt_r_n

Output

Z

High

Memory FCT245 Direction Xmit/Rcv Negated

Recommend external pull-up.

Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below.

output_clk

Output cpu_mas

terclk

High

Output Clock

Optional clock output.

PCI Interface

pci_ad[31:0]

I/O

Z

PCI

PCI Multiplexed Address/Data Bus

Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus

Master during writes; or the Data is driven by the Bus Slave during reads.

pci_cbe_n[3:0]

I/O

Z

PCI

PCI Multiplexed Command/Byte Enable Bus

Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable

Negated Bus driven by the Bus Master during the data phase(s).

pci_par

I/O

Z

PCI

PCI Parity

Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven

by the Bus Slave during the Read Data phase.

pci_frame_n

I/O

Z

PCI

PCI Frame Negated

Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates

the last datum.

pci_trdy_n

I/O

Z

PCI

PCI Target Ready Negated

Driven by the Bus Slave to indicate the current datum can complete.

pci_irdy_n

I/O

Z

PCI

PCI Initiator Ready Negated

Driven by the Bus Master to indicate that the current datum can complete.

pci_stop_n

I/O

Z

PCI

PCI Stop Negated

Driven by the Bus Slave to terminate the current bus transaction.

pci_idsel_n

Input

—

PCI Initialization Device Select

Uses pci_req_n[2] pin. See the PCI subsection.

pci_perr_n

I/O

Z

PCI

PCI Parity Error Negated

Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs.

pci_serr_n

I/O

Open-

collector

ZPCI

System Error

External pull-up resistor is required.

Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or

any other system error.

pci_clk

Input

—

PCI Clock

Clock for PCI Bus transactions. Uses the rising edge for all timing references.

Name

Type

Reset

State

Status

Drive

Strength

Capability

Description

Table 1 Pin Description (Part 2 of 7)