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Network Search Engine 32K x 72 Entries

Datasheet Brief 75N42102

SRAM Interface

The NSE provides all required address and control signals for a

glueless SRAM interface. The NSE provides a pipelined bypass path for

reads or writes to the external SRAM. The ASIC/FPGA handles the

pipelining of the data to and from the SRAM.

Registers

There are four basic types of registers supported:

segmentation of the entries, timing of outputs and the SRAM interface.

instructions by masking individual bits during a search.

a search from a Lookup operation.

Functional Highlights

Figure 1.1

Bus Interface

The NSE utilizes a dual bus interface consisting of the NSE Request

Bus and the NSE Response Bus.

The NSE Request Bus is comprised of the Command Bus and the

RequestDataBus. TheCommandBushandlestheinstructiontotheNSE

while the Request Data Bus is the main data path to the NSE.

The72bitbi-directionalRequestDataBusfunctionsasamultiplexed

address and data bus, which performs the writing and reading of NSE

entries, as well as presenting lookup data to the device.

The NSE Response Bus is comprised of an independent unidirec-

tional Index Bus which drives the result of the lookup (or index) to either

an SRAM device or an ASIC. In addition to driving the Index, the NSE

ResponseBusalsodrivestheassociatedSRAMcontrolsignals(

CE/OE,

and

WE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices.

Data and Mask Array

The NSE has Data cell entries and associ-

atedMaskcellentriesasshowninFig.1.1. This

combination of Data and Mask cell entries en-

ables the NSE to store 0, 1 or X, making it a full

ternary Network Search Engine. During a

lookup operation, both arrays are used along

with a Global Mask Register to find a match to a

requested data word.

A6457 drw 03

Da t a

Mask

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Synchronous Pipelined Burst SRAMs

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Command Bus

TheCommandBusloadsthe specificinstructionsintotheNSE.These

include:

A Read or Write instruction operates on a specified data entry, mask

entry, register or external SRAM.

AnSRAMNoWaitReadisaReadinstructiontoanexternalSRAMthat

canbepipelinedwithinaseriesofoperationsanddoesnotrequiretheuser

to wait for the Read to complete before loading the next instruction.

A lookup can be requested in 40-bit, 72-bit, 144-bit or 288-bit widths.

ThethreeSMDLLookupinstructionsoffertheabilitytosimultaneously

search in mutually exclusive databases which increases the search rate

up to 200 MSPS.