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PRELIMINARY
CY7C1410BV18
CY7C1425BV18
CY7C1412BV18
CY7C1414BV18
Document #: 001-07036 Rev. *B
Page 3 of 26
Logic Block Diagram (CY7C1412BV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
18
36
18
BWS[1:0]
VREF
18
A(19:0)
20
C
C
18
Write
Reg
Write
Reg
CQ
CQ
18
DOFF
Logic Block Diagram (CY7C1414BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
36
72
36
BWS[3:0]
VREF
36
A(18:0)
19
C
C
36
Write
Reg
Write
Reg
CQ
CQ
36
DOFF
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