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IDT82V2044BB Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT82V2044BB
Description  QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT82V2044BB Datasheet(HTML) 9 Page - Integrated Device Technology

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Pin Description
9
September 22, 2005
IDT82V2044
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
I
12
13
14
15
16
F4
F3
F2
F1
G3
MCn: Performance Monitor Configuration 3~0
In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select one transmitter or
receiver of channel 1 to 4 for non-intrusive monitoring. Channel 0 is used as the monitoring channel. If a
transmitter is monitored, signals on the corresponding pins TTIPn and TRINGn are internally transmitted
to RTIP0 and RRING0. If a receiver is monitored, signals on the corresponding pins RTIPn and RRINGn
are internally transmitted to RTIP0 and RRING0. The clock and data recovery circuit in Receiver 0 can
then output the monitored clock to pin RCLK0 as well as the monitored data to RDP0 and RDN0 pins. The
signals monitored by channel 0 can be routed to TTIP0/TRING0 by activating Remote Loopback in this
channel.
Performance Monitor Configuration determined by MC[3:0] is shown below. Note that if MC[2:0] = 000, the
device is in normal operation of all the channels.
An: Address Bus 4~0
When pin MODE1 is low, the parallel host interface operates with separate address and data bus. In this
mode, the signal on this pin is the address bus of the host interface.
OE
I
114
E14
OE: Output Driver Enable
Pulling this pin low can drive all driver output into high-Z for redundancy application without external
mechanical relays. In this condition, all other internal circuits remain active.
CLKE
I
115
E13
CLKE: Clock Edge Select
The signal on this pin determines the active edge of RCLKn and SCLK in clock recovery mode, or deter-
mines the active level of RDPn and RDNn in the data recovery mode. See 2.3 Clock Edges on page 14 for
details.
JTAG Signals
TRST
I
Pull-up
95
G12
TRST: JTAG Test Port Reset (Active Low)
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor
and can be left disconnected.
TMS
I
Pull-up
96
F11
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and it can be left disconnected.
TCK
I
97
F14
TCK: JTAG Test Clock
This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on the ris-
ing edges of TCK, while the data on TDO is clocked out of the device on the falling edges of TCK. This pin
should be connected to GNDIO or VDDIO pin when unused.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
TQFP144 PBGA160
MC[3:0]
Monitoring Configuration
0000
Normal operation without monitoring
0001
Monitor Receiver 1
0010
Monitor Receiver 2
0011
Monitor Receiver 3
0100
Reserved
0101
0110
0111
1000
Normal operation without monitoring
1001
Monitor Transmitter 1
1010
Monitor Transmitter 2
1011
Monitor Transmitter 3
1100
Reserved
1101
1110
1111


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