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IDT72200L15TPG Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72200L15TPG Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 11 page 6 COMMERCIALTEMPERATURERANGE IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 FEBRUARY 10, 2006 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 3. Write Cycle Timing NOTES: 1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. 2. The Clocks (RCLK, WCLK) can be free-running during reset. Figure 2. Reset Timing tRS tRSR RS REN tRSF tRSF EF, AE FF, AF Q0 - Q7 WEN tRSS tRSF tRSR tRSS OE = 1(1) OE = 0 2680 drw 04 WCLK D0 - D7 WEN FF tCLK tCLKH tCLKL tDS tENS tDH tENH tWFF tWFF DATA IN VALID RCLK (1) tSKEW1 REN NO OPERATION 2680 drw 05 |
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