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P4C198A-10JMB Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation

Part # P4C198A-10JMB
Description  ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS
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Manufacturer  PYRAMID [Pyramid Semiconductor Corporation]
Direct Link  http://www.pyramidsemiconductor.com
Logo PYRAMID - Pyramid Semiconductor Corporation

P4C198A-10JMB Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation

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P4C198/198L, P4C198A/198AL
Page 5 of 13
Document # SRAM113 REV A
READ CYCLE NO. 2 (ADDRESS Controlled)(5,6)
READ CYCLE NO. 3 (CE
CE
CE
CE
CE(12) Controlled)(5,7,8)
10. Read Cycle Time is measured from the last valid address
to the first transitioning address.
11. Transitions caused by a chip enable control have similar
delays irrespective of whether CE
1 or CE2 causes them
(P4C198A/L).
12. CE
1, CE2 for P4C198A/L.
Notes:
6. CE (CE
1 CE2 for P4C198A/L) and OE are LOW READ cycle.
7. OE is LOW for the cycle.
8. ADDRESS must be valid prior to, or coincident with CE (CE
1
and CE
2 for P4C198A/L) transition LOW.
9. Transition is measured ± 200mV from steady state voltage
prior to change, with loading as specified in Figure 1.


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