6.42

IDT71342SA/LA

High-Speed 4K x 8 Dual-Port Static RAM with Semaphore

Industrial and Commercial Temperature Ranges

9

CE or SEM

2721 drw 10

ADDRESS

R/

W

(4)

(4)

OE

(9)

(6)

(7)

(2)

(3)

(7)

(7)

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

NOTES:

1. R/

W or CE must be HIGH during all address transitions.

CE or R/W going HIGH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the

CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If

9. To access SRAM,

2721 drw 11

R/

W

ADDRESS

CE or SEM

(9)

(6)

(2)

(3)