5

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

FUNCTIONALDESCRIPTION

The 64x4FIFOisdesigned usinga dual port RAMarchitecture asopposed

to the traditional shift register approach. This FIFO architecture has a write

pointer, a read pointer and control logic, which allow simultaneous read and

writeoperations. ThewritepointerisincrementedbythefallingedgeoftheShift

In(Sl)control;thereadpointerisincrementedbythefallingedgeoftheShiftOut

(SO). The Input Ready (IR) signals when the FIFO has an available memory

location; Output Ready (OR) signals when there is valid data on the output.

Output Enable (

OE)providesthecapabilityofthree-statingtheFIFOoutputs.

FIFO RESET

The FIFO must be reset upon power up using the Master Reset (

MR)signal.

This causes the FlFO to enter an empty state, signified by Output Ready (OR)

being LOW and Input Ready (IR) being HIGH. In this state, the data outputs

DATA INPUT

Data is shifted in on the LOW-to-HlGH transition of Shift In (Sl). This loads

input data into the first word location of the FIFO and causes Input Ready (IR)

to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved to

thenextwordpositionandIRgoesHIGH,indicatingthereadinesstoacceptnew

data. If the FIFO is full, IR will remain LOW until a word of data is shifted out.

DATAOUTPUT

DataisshiftedoutontheHlGH-to-LOWtransitionofShiftOut(SO). Thiscauses

the internal read pointer to be advanced to the next word location. If data is

present, valid data will appear on the outputs and Output Ready (OR) will go

HIGH. Ifdataisnotpresent,ORwillstayLOWindicatingtheFIFOisempty. The

lastvalidwordreadfromtheFIFOwillremainattheFlFOsoutputwhenitisempty.

When the FIFO is not empty, OR goes LOW on the LOW-to-HIGH transition of

SO. Previous data remains on the output until the HIGH-to-LOW transition of

SO).

FALL THROUGH MODE

TheFIFOoperatesinafall-throughmodewhendatagetsshiftedintoanempty

FIFO. After a fall-through delay the data propagates to the output. When the

datareachestheoutput,theOutputReady(OR)goesHIGH. Fall-throughmode

also occurs when the FIFO is completely full. When data is shifted out of the full

FIFO, a location is available for new data. After a fall-through delay, the Input

Ready (IR) goes HIGH. If Shift In (SI) is HIGH, the new data can be written

to the FIFO.

SincetheseFlFOsarebasedonaninternaldual-portRAMarchitecturewith

A word may be written into the FIFO on a clock cycle and can be accessed on

the next clock cycle.

Figure 3. The Mechanism of Shifting Data Into the FIFO

NOTES:

1. IR HIGH indicates space is available and a SI pulse may be applied.

2. Input Data is loaded into the first word.

3. IR goes LOW indicating the first word is full.

4. The write pointer is incremented.

5. The FIFO is ready for the next word.

6. If the FIFO is full then the IR remains LOW.

7. SI pulses applied while IR is LOW will be ignored (see Figure 4).

Figure 2. Input Timing

SI

IR

INPUT DATA

2747 drw 06

SI

IR

INPUT DATA

STABLE DATA

(2)

(3)

(5)

2747 drw 07

(6)

(4)

(1)

(7)