7

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

Figure 8. Master Reset Timing

Figure 9. Output Enable Timing, IDT72403 Only

NOTE:

shown in Figure 1.

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IR

SI

SO

OR

MR

IR

SI

SO

OR

MR

SHIFT IN

INPUT READY

DATA IN

MR

OUTPUT READY

SHIFT OUT

DATA OUT

NOTE:

1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.

Figure 10. 128 x 4 Depth Expansion

SI

SO

OR

(1)

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DATA OUTPUT

DATA VALID

HZOE

t

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OE

DATA OUT

NOTE:

1. FIFO initially empty.

MR

IR

OR

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SI

DATA OUTPUT

(1)

(1)

NOTE:

1. Worst case, FIFO initially full.