MILITARY AND COMMERCIAL

TEMPERATURE RANGES

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

4

560

Ω

30pF*

1.1K

Ω

5V

OUTPUT

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Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

OutputReferenceLevels

1.5V

OutputLoad

See Figure 1

ALL INPUT PULSES:

SIGNAL DESCRIPTIONS

INPUTS:

Data input lines. The IDT72401 and IDT72403 have a 4-bit data input.

CONTROLS:

SHIFT IN (SI)

Shift In controls the input of the data into the FIFO. When SI is HIGH, data

SHIFT OUT (SO)

ShiftOutcontrolstheoutputofdataoftheFIFO. WhenSOisHIGH,datacan

MASTER RESET (

MR)

Master Reset clears the FIFO of any data stored within. Upon power up, the

FIFO should be cleared with a

MR. MR is active LOW.

INPUT READY (IR)

WhenInputReadyisHIGH,theFIFOisreadyfornewinputdatatobewritten

toit.WhenIRisLOWtheFIFOisunavailablefornewinputdata. IRisalsoused

to cascade many FlFOs together, as shown in Figures 10 and 11.

OUTPUT READY (OR)

OR is LOW, the FIFO is unavailable for new output data. OR is also used to

cascade many FlFOs together, as shown in Figures 10 and 11.

OUTPUT ENABLE (

OE) (IDT72403 ONLY)

Output enable is used to read FIFO data onto a bus.

OE is active LOW.

OUTPUTS:

Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output.

or equivalent circuit

Figure 1. AC Test Load

*Including scope and jig

Symbol

Parameter

Conditions

Max.

Unit

InputCapacitance

5

pF

OutputCapacitance

7

pF

1. Characterized values, not currently tested.

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GND

3.0V

90%

10%

90%

10%

<3ns

<3ns

AC TEST CONDITIONS

CAPACITANCE