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IDT72401L25P Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72401L25P Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 9 page MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT72401/72403 CMOS PARALLEL FIFO 64 x 4, 64 x 5 4 560 Ω 30pF* 1.1K Ω 5V OUTPUT 2747 drw 05 Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V OutputReferenceLevels 1.5V OutputLoad See Figure 1 ALL INPUT PULSES: SIGNAL DESCRIPTIONS INPUTS: DATA INPUT (D0-3) Data input lines. The IDT72401 and IDT72403 have a 4-bit data input. CONTROLS: SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-3 lines. SHIFT OUT (SO) ShiftOutcontrolstheoutputofdataoftheFIFO. WhenSOisHIGH,datacan be read from the FIFO via the Data Output (Q0-3) lines. MASTER RESET ( MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a MR. MR is active LOW. INPUT READY (IR) WhenInputReadyisHIGH,theFIFOisreadyfornewinputdatatobewritten toit.WhenIRisLOWtheFIFOisunavailablefornewinputdata. IRisalsoused to cascade many FlFOs together, as shown in Figures 10 and 11. OUTPUT READY (OR) When Output Ready is HIGH, the output (Q0-3) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. OR is also used to cascade many FlFOs together, as shown in Figures 10 and 11. OUTPUT ENABLE ( OE) (IDT72403 ONLY) Output enable is used to read FIFO data onto a bus. OE is active LOW. OUTPUTS: DATA OUTPUT (Q0-3) Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output. or equivalent circuit Figure 1. AC Test Load *Including scope and jig Symbol Parameter Conditions Max. Unit CIN InputCapacitance VIN = 0V 5 pF COUT OutputCapacitance VOUT = 0V 7 pF NOTE: 1. Characterized values, not currently tested. 2747 drw 04 GND 3.0V 90% 10% 90% 10% <3ns <3ns AC TEST CONDITIONS CAPACITANCE (TA = +25°C, f = 1.0MHz) |
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