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IDT72V3666L10PF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V3666L10PF Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 39 page 2 COMMERCIALTEMPERATURERANGE IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 SRAMFIFOsonboardeachchipbufferdatabetweenabidirectional36-bitbus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receivesdata.) FIFOdatacanbereadoutofPortBandwrittenintoPortCusing either18-bitor9-bitformatswithachoiceofBig-orLittle-Endianconfigurations. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for DESCRIPTION TheIDT72V3656/72V3666/72V3676arepinandfunctionallycompatible versions of the IDT723626/723636/723646, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic, high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memorywhichsupportsclockfrequenciesupto100MHzandhasreadaccess times as fast as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port PIN CONFIGURATION TQFP (PK128-1, order code: PF) TOP VIEW W/ RA CLKB 4665 drw02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ENA CLKA GND A35 A34 A33 A32 Vcc A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/ FWFT GND A22 Vcc A21 A20 A19 A18 GND A17 A16 A15 A14 A13 Vcc A12 GND A11 A10 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 PRS2/RT2 C17 C16 C15 C14 MBC RTM C13 C12 C11 C10 C9 C8 C7 C6 SIZEB GND C5 C4 C3 C2 C1 C0 GND B17 B16 B15 B14 B13 B12 GND B11 B10 INDEX SIZEC VCC VCC LOOP |
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