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IDT72T54252L5BB Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT72T54252L5BB
Description  2.5V QUAD/DUAL TeraSync??DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72T54252L5BB Datasheet(HTML) 9 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSyncDDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
TCK(3)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
INPUT
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the
rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used
this signal needs to be tied to GND.
TDI(3)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Input
INPUT
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left
unconnected.
TDO(3)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Output
OUTPUT
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the
Instruction Register, ID Register and Bypass Register. This output is high impedance except
when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(3)
JTAG Mode Select
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left
unconnected.
TRST(3)
JTAG Reset
HSTL-LVTTL
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
INPUT
automaticallyresetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGH
for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be
in high-impedance. If the JTAG function is used but the user does not want to use
TRST,thenTRST
canbetiedwith
MRStoensureproperFIFOoperation.IftheJTAGfunctionisnotusedthenthissignal
needs to be tied to GND. An internal pull-up resistor forces
TRST HIGH if left unconnected.
WCLK0/1/2/3
Write Clock 0/1/2/3
HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the write port. If Dual mode
INPUT
is selected then WCLK1 and WCLK3 are not used and should be tied to GND. In SDR mode data
will be written on the rising edge of WCLK when
WENandWCSareLOWattherisingedgeofWCLK.
In DDR mode data will be written on both rising and falling edge of WCLK when
WEN and WCS are
LOW at the rising edge of WCLK.
WCS0/1/2/3
WriteChipSelect
HSTL-LVTTL These are the write chip select inputs corresponding to each of the four FIFOs on the write port. This
INPUT
pin can be regarded as a second write enable input, enabling/disabling write operations.
WCS is
only sampled on the rising edge of WCLK. If Dual mode is selected then
WCS1 and WCS3 are not
used and should be tied to VCC.
WDDR
Write Port DDR
CMOS(2)
Duringmasterreset,thispinselectstheinputporttooperateinDDRorSDRformat.IfWDDRisHIGH,
INPUT
then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.
If WDDR is LOW, then a word is written only on the rising edge of the appropriate WCLK0, 1, 2 and
3 inputs.
WEN0/1/2/3
Write Enable 0/1/2/3 HSTL-LVTTL These are the write enable inputs corresponding to each of the four FIFOs on the write port. In SDR,
INPUT
when this signal (and
WCS) are LOW data on the databus will be written into the FIFO memory on
every rising edge of WCLK. In DDR mode, data will be written on both rising and falling edges of
WCLK. Note in DDR mode the
WEN and WCS are only sampled on the rising edge of WCLK. New
data will always begin writing from the rising edge, not the falling edge of WCLK. If Dual mode is
selected then
WEN1 and WEN3 are not used and should be tied to VCC.
VCC
+2.5V Supply
Power
These are VCC core power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
OutputRailVoltage
Power
This pin should be tied to the desired voltage rail for providing to the output drivers. Nominally 1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
GND
Ground Pin
Ground
These ground pins are for the core device and must be connected to the GND rail.
Vref
Reference voltage
Power
This is a Voltage Reference input and must be connected to a voltage level determined in the Voltage
Recommended DC Operating Conditions section. This provides the reference voltage when using
HSTL class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
Symbol
Name
I/O Type
Description
PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. All unused outputs may be left floating.
2. All CMOS pins should remain unchanged. CMOS format means that the pin is intended to be tied directly to VCC or GND and these particular pins are not tested for VIH or VIL.
3. These pins are for the JTAG port. Please refer to pages 27-31 and Figures 7-9.


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