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IDT79RC64V474-200DPI Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT79RC64V474-200DPI Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 25 page  3 of 25 April 10, 2001 RC64474™ RC64475™ A secure user processing environment is provided through the user, supervisor, and kernel operating modes of virtual addressing to system software. Bits in a status register determine which of these modes is used. If configured for 64-bit virtual addressing, the virtual address space layout becomes an upwardly compatible extension of the 32-bit virtual address space layout. Figure 1 is an illustration of the address space layout for the 32-bit virtual address operation. The RC64474/RC64475’s Memory Management Unit (MMU) controls the virtual memory system’s page mapping and consists of a translation lookaside buffer (TLB) used for the virtual memory-mapping subsystem. This large, fully associative TLB maps 96 virtual pages to their corresponding physical addresses. The TLB is organized as 48 pairs of even-odd entries and maps a virtual address and address space identi- fier into the large, 64GB physical address space. To assist in controlling the amount of mapped space and the replacement characteristics of various memory regions, two mechanisms are provided. First, the page size can be configured on a per-entry basis, to map a page size of 4KB to 16MB (in increments of 4x). The second mechanism controls the replacement algorithm, when a TLB miss occurs. A random replacement algorithm is provided to select a TLB entry to be written with a new mapping; however, the processor provides a mechanism whereby a system specific number of mappings 0xFFFFFFFF 0xE0000000 Kernel virtual address space (kseg3) Mapped, 0.5GB 0xDFFFFFFF Supervisor virtual address space (sseg) Mapped, 0.5GB 0xC0000000 0xBFFFFFFF 0xA0000000 Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0x9FFFFFFF 0x80000000 Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0x7FFFFFFF 0x00000000 User virtual address space (useg) Mapped, 2.0GB Figure 1 Kernel Mode Virtual Addressing (32-bit Mode) can be locked into the TLB and avoid being randomly replaced, which facilitates the design of real-time systems, by allowing deterministic access to critical software. The TLB also contains information to control the cache coherency protocol, and cache management algorithm for each page. However, hardware-based cache coherency is not supported. The RC64474 and RC64475 enhance IDT’s entire RISCore4000 series through the implementation of features such as boundary scan, to facilitate board level testing; enhanced support for SyncDRAM, to simplify system implementation and improve performance. The RC64474/475 processors offer a direct migration path for designs based on IDT’s RC4640/RC4650 processors2, through full pin and socket compatibility. Also, full 64-bit-family software and bus- protocol compatibility ensures the RC64474/475 access to a robust development tools infrastructure, allowing quicker time to market. Development Tools An array of hardware and software tools is available to assist system designers in the rapid development of RC64474/475 based systems. This accessibility allows a wide variety of customers to take full advan- tage of the device’s high-performance features while addressing today’s aggressive time-to-market demands. Cache Memory To keep the RC64474 and RC64475’s high-performance pipeline full and operating efficiently, on-chip instruction and data caches have been incorporated. Each cache has its own data path and can be accessed in the same single pipeline clock cycle. The 16KB two-way set associative instruction cache (I-cache) is virtually indexed, physically tagged, and word parity protected. Because this cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing both operations to occur simultaneously. The instruction cache provides a peak instruction bandwidth of 1000MB/sec at 250MHz. The 16KB two-way set associative data cache (D-cache) is byte parity protected and has a fixed 32-byte (eight words) line size. Its tag is protected with a single parity bit. To allow simultaneous address transla- tion and data cache access, the D-cache is virtually indexed and physi- cally tagged. The data cache can provide 8 bytes each clock cycle, for a peak bandwidth of 2GB/sec. To lock critical sections of code and/or data into the caches for quick access, a “cache locking” feature has been implemented. Once enabled, a cache is said to be locked when a particular piece of code or data is loaded into the cache and that cache location will not be selected later for refill by other data. This feature locks a set (8KB) of Instructions and/or Data. Table 2 lists the RC64474/475 Instruction and data cache attributes. 2. To ensure socket compatibility, refer to Table 8 and Table 9 at back of data sheet. |
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